AMD challenges Intel with an 84-core Epyc processor aimed at telcos, edge
The Register
February 25, 2026
AI-Generated Deep Dive Summary
AMD has unveiled its latest 84-core Epyc processor, part of the Zen 5 architecture, designed to challenge Intel in the telecommunications and edge computing markets. Codenamed Sorano, this chip replaces AMD's older Siena Epyc series and features a significant jump in core count from 64 to 84 cores while maintaining a power efficiency of just 225 watts. The processor also boasts a 512-bit vector instruction path and optimizations for low-density parity check (LDPC) decoding, which reduces latency and enhances forward error correction in 5G networks. These improvements make Sorano ideal for virtualized radio access network (vRAN) applications, a critical component of modern 5G infrastructure.
The chip's design targets telecom equipment manufacturers like Samsung, Ericsson, and Nokia, who are increasingly relying on server-grade processors for their vRAN solutions. AMD's focus on high core density and low power consumption has caught the attention of these companies, offering a compelling alternative to Intel's Xeon 6E and Xeon 6 SoC platforms. While Intel's chips cater to specific RAN requirements with up to 144 cores, AMD's Sorano aims to deliver better performance per server by freeing up compute resources for additional processing tasks.
Despite its strengths, Sorano faces competition from Intel's specialized vRAN-Boost technology and its Xeon 6 SoC series. Intel's approach emphasizes core density and onboard accelerators for crypto, AI, and media transcoding, which aligns with Nokia's preference for their network appliances. However, AMD's ability to pack more cores into a lower power envelope could give it an edge in certain scenarios, particularly for telcos seeking efficient and scalable solutions.
AMD's Sorano represents the pinnacle of its Zen 5 lineup, with plans for Venice CPUs, featuring up to 256 Zen 6 cores per socket, set to debut later this year. This new generation will also include Venice-X, a high-performance computing variant utilizing 3D V-Cache technology for enhanced L3 cache
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Originally published on The Register on 2/25/2026